Indentation Water bumping at a wafer-level packaging site
Indentation WAFER-BUMPING.COM
A new website for wafer bumping, wafer level packaging…
Wafer-Bumping provides engineering solutions and technical consulting services.
DESIGN AND MASK LAYOUT TO PACKAGING
- Layouts for bumping your wafers at your foundry
- Potential vendors can be evaluated using mask sets
- Mask sets are used for internal process development
NEW VALUE
- Evaluation of new materials at a packaging house
- Improvement of existing processes
- New wafer-level packaging processes developed
THIN-FILM MATERIALS
- Selection of inorganic dielectrics or polymers
- Selecting the right metallization scheme for UBM and RDL
- Selection of solders with and without Pb
THIN-FILM PROCESSES
- Equipment and processes that sputter
- Wet and plasma etching of metals, polymers and silicon
- Photolithography
Last update Oct. 1, 2003
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Materials
How to Choose Bumping Materials
Our knowledge in thin film materials, polymers and other related fields will help you to choose the best wafer bumping supplier for your application. The process of developing bumping or WLP begins with an in-depth evaluation of all potential materials and their effects on the process. Also, consider the implications for long-term reliability. Our years of experience in thin film materials will help you achieve your goals faster than the competition.
Polymers
There are many polymers that can be used to pack wafer-level packaging. Some of these polymers have been used for years as a passivation layer on semiconductor wafers. Comparing polymers involves looking at their physical, chemical, and other properties. This can be used to help choose or compare them. It is important to be precise in your selection criteria. In WLP, the thin layer of polymer spun on the wafer will serve as the only protection for the chip from the environment.
Many of the so-called low-k dielectrics intended for wafer inner-layer-dielectric (ILD) are not suitable for packaging because of their inability to form layers thicker than one micron without cracking. Poly-silsesquioxane, for example, has a positive dielectric constant and cracks when it builds layers thick enough to be packaged. SiO2 and Si3N4 are susceptible to similar problems, or have low deposition rates making them unsuitable for packaging.
Dielectric selection is not an exact science. It involves many compromises between competing, often contradictory, requirements. Outstanding material properties, for example, can conflict with substrate processability and adhesion. Problems may arise from adhesion of polymers to metals or other dielectrics.
Our experience in multi-layer metalization devices has been invaluable to our clients.
Metals
For years, we have used interconnect metallization that is based on aluminum, copper, and gold. The purpose of your project, as well as the available equipment, will determine which method you choose. Operation at high speeds or with low levels of signals might require low interconnect noises and losses. This is why thick copper interconnect is preferred over thin aluminum.
When choosing an interconnect material, there are many other factors to consider. A diffusion barrier or adhesion metal might be required. It is important to consider the selectivity of etchants as well as the possible damage to some chemistry to polymers (including photoresist). Handbook etching recipes are not useful because they don’t account for the electro-chemistry that occurs when dissimilar metals come in contact.
The desired reliability over the long-term is what will dictate which RDL metallurgy to choose. Over the years, several reliable systems have been proven to be effective. You can also choose nickel or cobalt alloys, or pseudo-alloys, for reliability. The final decision rests with other factors like etching or deposition.
Solders
Any soft solder can be used with almost any desired polymer for WLP. Temperatures, even 95-5 Pb temperatures, are not an issue. The end use dictates the choice of solder, not bumping fabrication issues.
Wafer-Bumping.com:
John Davis, a Tempe (AZ) resident, started Wafer-Bumping in 2022 to offer advanced electronic polymer processing technology services to the advanced packaging engineering community.
Wafer-Bumping’s goal is to speed up the design, development and production of advanced packaging technologies.
Summary of Experience
John has many years experience in photolithography, sputtering and other microelectronics fabrication processes, as well as thin-film optics.
John began developing projects that used polyimides to create thin-film products as dielectrics in the 70’s. At the time, work with polyimides was limited to a few large research labs such as RCA, Bell Labs, IBM, TI or Hitachi that applied for a patent in 1972 using PIQ (Poly-Isoindolo-Quinazolinedione) as ILD (Inner Layer Dielectric) to build bipolar integrated circuits. John has been working with many different types of high-temperature polymers, including experimental and commercial polyimides.
John established his first photolitho thin film R&D and sputtering lab at GTE Lenkurt in Vancouver. He built experiments using cross-over polyimide in this lab. These circuits used thick-film and thin-film hybrid technology and flip-chip semiconductors from Cherry’s and Motorola. This experiment was designed to create a reliable and simple interlayer dielectric that can be used in interconnects between two layers.
John joined the magnetic thin-film development group of Memorex Santa-Clara, CA in 1977. His responsibilities included the development of polyimide insulated copper coils as well as finding suitable ceramic materials for substrate. Because it was non-porous, Alumina Titanium Carbidide was chosen. However, there were some challenges as its sole use was for making tool bits for metal cutting.
John had already built four layers of polyimide and four interconnect copper layers thin-film flip-chip memory module for Hughes Aircraft Electro-Optics Division in 1985. In late 1986, this work was used to plan a multichip module business. The company was founded with bare walls from Ventura’s (CA), warehouse on January 1, 1987. An aerospace company received silicon substrate prototypes by June 1987.
MCM-D was built in late 1980’s to match the clocking speeds of semiconductors, reduce power dissipation in I/O driver with matched impedance and reduce circuit volume. There is a significant push to lower fabrication costs in order to meet the needs of the consumer markets. Most of the early interest in MCM-D was focused on satellites with a payload of $10,000 per ounce. Advanced missiles and aircraft weaponry were more expensive.
His work in thin-film led to the construction of half a dozen clean rooms and the development of sputtering equipment as well as control software. He also worked on thin-film optics and magneto-optics to record data. His thesis was about the fabrication of eeproms using trapping charges between two dielectric layer. Plasma anodizing a thin aluminum layer deposited on top of silicon was used to create the dielectric layers. Plasma anodization was used until the aluminum formed a stochiometric layer of aluminum oxide with a thin layer silicon anodized beneath it.
John is the holder of five US patents, and is also the author or co-author of more than 60 technical papers or presentations at technical meeting.
John received a Bachelor’s and Master of Applied Sciences degrees in Electrical Engineering at the University of British Columbia, Vancouver, Canada. His thesis was entitled “The Preparation and Properties of rf–Plasma Anodized SIO2 & AL2O3 Thinfilms.”
Al-Si Schottky Photodiodes
Confidential work:
Without your written consent, we will not reveal the existence of a relationship with you company or make use of your company name in advertising. We expect to sign Non-Disclosure Agreements in order to protect our client’s confidential Intellectual Property (IP).
NDAs are usually secured at the corporate level. They must be signed before any confidential or proprietary information can be shared. After the NDA is signed, any exchange of confidential or proprietary information should be documented in a document called a Confidential Information Transmittal Records (CITR).
Services that can help you solve your problems
We offer expertise in WLP and bumping projects
Wafer-Bumping is able to help you solve your fabrication problems with its unique combination of thin film, polymers materials, and process expertise. All aspects of flip-chip packaging and wafer-level packaging are covered by us.
- Choose a bumping vendor
- Layout and design of interconnect
- New bumping methods are being developed
- Troubleshoot manufacturing problems
- Troubleshoot reliability problems
- Select appropriate fab equipment
- New Business Engineering Development
Although flip chips have been around for 40 years, there are still challenges in bumping wafers. The bumping cost remains high and some facilities have poor yields and reliability. These problems are rarely caused by one factor. Recurrent difficulties can be caused by inapropriate equipment, unsuitable processing, poor materials selection, or unreliable plasticmers.
How to Choose a Bumping Vendor
Wafer-Bumping is able to help you choose a vendor. Our test patterns can be used to help you evaluate and qualify manufacturing processes, reliability, and to compare the reliability of different parts and their reliability. Combining our test patterns with the PCB allows you to compare all sources that meet the same criteria. The mask sets indicate the tolerances that can reasonably be expected from a particular source. Wafers can be secured from different processing lots to ensure consistency in production.
Layout and Design of Interconnect
The development of a flip-chip-based product requires a combination design, manufacturing knowledge and materials selection. We can help control parasitic capacitance or impedance of transmission line. We can help you with the fabrication of masks. We can accommodate any design requirements that you may have.
Bumping Process
Wafer-Bumping’s knowledge of equipment, processes, and materials can help you speed up your advanced packaging design. Our expertise can help you distinguish between trouble-free and functional manufacturing. We also have the ability to identify recurring problems that are not easily solved. Wafer-Bumping will help you design the process. We can provide you with stable materials and well-characterized fabrication steps. This will allow you to meet your deadlines in launching new flip-chipped semiconductor products. Our staff can be guided by our knowledge of wafer manufacturing processes. You can avoid costly delays when introducing products by using our expertise in testing and bumping WLP.
Troubleshoot Fabrication Problems
Because we are familiar with most of the problems that may arise during fabrication, we can quickly identify fabrication issues. We can help you find the root cause of defects. We are familiar with many lab techniques that can help you identify the root cause of problems, such as equipment malfunctions, material failures, or operator errors.
Resolve Reliability Problems
We are familiar with the failure modes of many polymers. Expertise in thin film metallurgy, deposition techniques and other related areas. We are familiar with the potential problems they can cause. We are able to help you differentiate between process-rooted and random failures.
Select Fab Equipment
It is important to remember that WLP equipment has different requirements than semiconductor manufacturing. Poor choices could have a devastating impact on your manufacturing operations for many years. Wafer-Bumping with thin film equipment can help you make the right choice.
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Figure 5 of US Patent #3.292, 240, August 8, 1963, McNutt Davis, and Mones. It was assigned to IBM.
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Masks for Wafer Level Packaging and Bumping
We have accumulated a large number of test patterns over the last 20 years and combined them into a mask set. The masks are versatile and economical photolitho tools that can be used for process development, validation or reliability qualification.
Masks allow for quick and detailed investigation of the boundaries of processes. No matter what fabrication process you use, our patterns can be used. They can be used with any dielectric polymer that is suitable for wafer passivation.
It is expensive to create photolitho test sets from scratch. First, determine the parameters that need to be monitored in process development. The next step is to establish a test strategy to monitor parts during fabrication and reliability testing. Before any fabrication can begin, it is necessary to define suitable patterns, convert them into a physical layout, and document them.
This can be done quickly, saving you many design iterations and providing you with a roadmap to development. The masks can be used to assess and check the capabilities of vendors. They can be used by a polymer user as well as a semiconductor house that needs to evaluate the quality of bumping from packaging companies.
For reliability testing, match the PCB
Final reliability testing involves mounting WLP Flip-chips on printed circuit board for temperature cycling, humidity test etc. The PCB should provide suitable connections for testing the parts under bias. It must be possible to access the test points on the PCB to identify the failure modes and where they are located. The PCB must also be manufactured.
Although PCB fabrication doesn’t require advanced design capabilities, it does take time and energy that could be better used for process development. Our company offers a cost-effective way to speed up your accelerated ageing tests and save you both time and money.
Chrome masks
Wafer-Bumping is able to supply you with a GDSII database or ready-to-use chrome mask sets that are specific to your mask aligning machine. You can specify a variety of mask materials or polarity to suit your needs.
Chrome masks are necessary for bumping at the back-end when using proximity aligners. Chrome blanks are able to produce masks with high resolution and a sharp edge. They also have a long shelf life. Chrome is preferred to other materials that are opaque to ultraviolet light. Iron-oxide masks have the advantage of being semitransparent in visible spectrum. This allows for alignment of dark fields masks. Iron oxide masks can be fragile and prone to pinholes. Worse, they also degrade with time. They eventually leak ultraviolet through the opaque areas, often without the knowledge or consent of the mask aligner operator. This can have disastrous consequences for process control. Even though they are more expensive, chrome masks still remain the cornerstone of the industry.
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Printed Circuit Boards
PCB for WLP Reliability Testing
To test the reliability of the wafers, they must be diced after the process optimization phase is completed.
We have created boards that match the footprints of test dies to facilitate testing. The test points are distributed in an easy to use pattern so that probing is simple. The boards can be plugged to conduct electrically biased reliability testing. MIL-spec connectors are compatible with the contact pattern. They can withstand prolonged exposure to high temperatures. To connect the wiring harness directly to the board, soldering points can also be provided. This is helpful when bias tests are being performed in high humidity environments.
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Resources
The Wafer-Bumping resource page’s goal is to offer links that can be useful in your search of equipment, services, or knowledge.
We don’t have the ambition to create an encyclopedia, nor do we want to meet all your needs. We have created our resource pages to share some useful links we found during our work.
links for chemists provides an index of web-based chemistry resources. This website is The University of Liverpool’s Department of Chemistry.
- Vermont Safety Information Resources
A great source for hundreds chemical MSDS
OSHA, EPA Regulations
- National Institute of Standards and Technology
High Speed Microelectronics – A large collection papers on high speed, rf and transmission line papers for silicon wafers.
MOSIS is a low cost prototyping and small volume production service for VLSI Circuit Development. MOSIS has manufactured more than 50,000 circuits for companies, government agencies, research, educational, and other institutions all over the globe since 1981.
A directory of technology and scientific sources.
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Here are some links to technical publications
Below are a few links to magazines or technical journals that may be of interest to EE and process engineers involved in advanced packaging.
The IBM Journal of Research and Development covers all aspects of computer-related technologies. Articles reviewed from IC design, manufacturing, packaging, physics, mathematics, or software development.
SemiconductorFabtech is an electronic magazine that covers semiconductor technology and packaging from an European perspective. You can view the contents, abstracts, selected articles, and complete editions. You can browse through the abstracts for the most recent issue.
Monthly publication of the American Institute of Physics (AIP) is The Industrial Physicist. The American Institute of Physics publishes it monthly. It gives insight into advanced research and development in industrial establishments. A great web site for product development engineers and applied research. The Dec./January 2005 issue of the magazine saw the end of publication.
HTML3_ HTML4_ Physics Today The core publication of American Institute of Physics is HTML3_ HTML4_ HTML5_ HTML6_ HTML7_ HTML8_ Physics Today . It has been published every month for over 50 years. Its purpose is to inform readers about science and its place within the world. You will find news stories, analysis, and authoritative features, as well as a forum for ideas exchange.
Microwave Journal EE publication devoted to microwave circuit design techniques. The microwave frequencies of yesterday were only available to high-end radars and trunk line communication circuits. Today, microwave frequencies are used in consumer products such as cellphone handsets, wireless networks, and cell phones. They will soon be used in computer communication buses.
Journal of Corrosion Science and Engineering This British journal is freely accessible and contains papers that can be used by anyone interested in the long-term reliability of thin films and other reliability issues caused corrosion.
Here are some links to educational websites

MIT’s OpenCourseWare
Open educational resource that is free and available to all self-learners from around the globe. OCW supports MIT in its mission to improve knowledge and education and serve the 21st-century world. It is in keeping with MIT’s core values of innovation, excellence, and leadership. MIT OCW provides 500 courses from all five MIT schools and 33 academic disciplines. View the complete courses list

Dilbert
United Media’s (UM), a syndication company that focuses exclusively on creative content, will help you to deepen your engineering knowledge.
Technology Files
“Intelligence does not refer to the ability to store information but rather to be able to identify where it is.
Albert Einstein
The web and search engines can help…
Recent packaging papers:
These papers are in Adobe Acrobat pdf format.
” Applications from FTIR to Advanced Packaging final John J. H. Reche
This paper was presented at the 11th Meeting of The Symposium on Polymers for Microelectronics At Winterthur, Wilmington Delaware May 5, 6, and 7, 2004.
” Wafer-level packaging with bump-on-polymer structuring” John J. H. Reche, and Deok-Hoon K
This paper is the “Introductory Invited Article” in the June 2003 issue Microelectronics. (Vol. 43, Issue 6 , June 2003, Pages 879-894). This paper describes the new technology that was introduced by Kulicke & Soffa (K&S), Flip Chip Division (formerly Flip Chip Technology) and marketed as Spheron(TM). The WLP technology is based on a polybenzoxazole, (PBO). This polymer not only has excellent reliability, but it also offers exceptional manufacturability. Excellent reliability results are achieved due to the polymer’s high mechanical toughness, high length, and excellent adhesion with organic and inorganic material.
You can request a paper copy by email, or you can use the feedback page.
” Wafer Thinning and Trough-Silicon Vias-The path to 3-D Wafer Level Packaging” John J. H. Reche
This paper was presented at the IEEE CPMT Silicon Valley Chapter meeting in Santa Clara CA on May 10, 2000.
A free update to Adobe’s Acrobat reader Version 7.0 can be found on their website for many operating systems.
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Circuits with high bandwidth
High frequencies and clock rates
Digital electronic systems require increasingly complicated interconnections between primary switch devices, i.e. The transistors and the user interface. The clocking rates of ICs can reach the low gigahertz range. The communication bandwidth between and outside chips is still an order of magnitude smaller and hinders the maximum utilization of the chips’ potential. The I/O drivers and interconnect cables between the chips are another factor that cannot be ignored. While most IC designers have focused on reducing power requirements for the chip logic, little has been done to improve power dissipation within the interconnect circuitry.
WLP and placing bumps on top of the polymer are crucial elements to ease interchip bus speed bottlenecks as well as minimize power dissipation. WLP offers many advantages. It reduces the length and capacitance of interconnects, which is a significant benefit to high speeds. This is because the bumps are placed over a thick layer polymer. This technology also allows you to control the impedance of transmission lines.
An article in the consumer-oriented PC Magazine featured, dated February 27, 2003, claimed that “confidential Intel documents” revealed Intel’s roadmap for flip-chips. This technology was published by Intel a while back, but is now available to the general public.
To overcome the current bottleneck caused by outside semiconductor dies,
PC bus speed are expected to rise to 800 MHz within the next 4-5 years. The PCs have been using bus speeds of around 100 MHz for years with clock rates in the GHz range. Intel is moving ahead with technology that will allow them to better match the clocking speeds of their semiconductor chips. Bus speeds of up to 10 Mbps will require controlled impedance on the circuit boards and interfaces.
“Tejas”, a successor to the Pentium 4-style “Prescott”, will be officially launched in the second quarter of 2004. It will include Flip-Chip Technology on Organic Pin Grid Array Packages, which was published in the Intel Technology Journal 3rd quarter 2000. This article, entitled “Flip Chip Technology on Organic Pin Grid Array Packages”, demonstrates the use of C4 bumped dens.
rf Applications
For this purpose, rf is defined as analog signals exceeding a few hundred megahertz. For the proliferation of cellular communication equipment, the low-power, short-range, rf communication like Bluetooth and Ultrawideband or wireless networks, high frequency, low noise, low lost, record low cost interconnect is required. In rf applications, the need to create bumps on top of a capacitive polymer layer is more important than in digital.
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Metrology of Thin Films
Measurement of film properties
FTIR
The Fourier transform infrared (FTIR) spectroscopy can be used to identify and characterize organic molecules. IR spectrum can identify chemical bonds, molecular structures of polymers and other materials. Infrared light can only pass through materials that have bonds. They will absorb light at a frequency equal to the material’s characteristic vibrational frequency. If there are bonds, peaks will be visible in the absorption spectrum when you scan a range of IR wavelengths. These absorption spectra can be used to identify molecules and the formation, destruction, straining, or straining bonds due to processing or mechanical stressing. Polymer materials can undergo changes in their molecular structures when they are heated, exposed or mixed. This affects the IR “signature”. An FTIR can track all these changes.
FTIR is not only a research tool. It is also one of the most cost-effective analytical tools that should be used by any manufacturing or R&D facility handling thin-film polymers. FTIR is a tool that can be used to inspect materials during incoming inspection. It also allows you to monitor the process and evolution of polymers as they cure. It provides non-destructive information about daily processing variations and degradation due to strained bonds or oxidation. FTIR can be used to identify and clarify processing problems, identify contaminants, identify byproduct materials that evolve during curing polymers, or identify a competitor’s product.
Measuring adhesion
Adhesion is a hard physical property to measure. If adhesion of thin films can only be predicted, it will affect device reliability. Despite its fundamental importance in device fabrication, it is not common to perform quantitative adhesion measurements in manufacturing. Although adhesion tests can measure force, energy, or strength, they are often difficult to interpret in a manufacturing environment. Also, it is not possible to find a universal measurement that will work in all circumstances.
Scotch Test
The “Scotch” qualitative adhesion test, which was inherited from the Military Standard specifications, is not reliable and provides only a low adhesion threshold. It was discovered that the film could not be peeled and the bonding was weak. This makes it completely unacceptable.
Peel Test
The 180o peel test (per ASTMD903-98 is another qualitative test that produces a number. It’s superior to the “Scotch tape” test. The film to be tested is cut into a few millimeters wide strips. Next, apply a force perpendicularly to the surface in a slow, uniform motion. Although the test is reproducible and quantitatively understandable, it can be used widely in the PCB industry. However, thin films may pose practical problems.
Other common adhesion testing techniques include the stud pulling, blister, interfacial and indenture, scratch, and the blister tests.
Stud Pull Test
The stud pull test involves bonding a metal DUT (Device Under Test), with epoxy. The stud is pulled slowly until it fails. The value of the breaking force used to separate the substrate and film under test is what you get. To determine the cause of failure and to interpret the results, it is necessary to examine the surfaces that have been broken. The film-substrate interface may be the cause of delamination. It may also have suffered cohesive failure. The substrate might have fractured. Or, it may have been in the epoxy or stud. This method is able to produce a repeatable tensile strength despite all its flaws. It provides an independent numerical value for the force per unit area required to achieve tensile failure.
Test Blister
To test the film for blisters, you need to etch a hole in the substrate. The film is then tucked over the hole. The film is then subjected to hydrostatic pressure from the substrate until it tears or delaminates. Hydrostatic force and work on the back of the film can calculate the energy required to separate the film and its substrate. This technique is not easy to use and is best left for theoretical research.
Test for indentation
Indentation testing presses a pointed stylus onto the film until the film buckles under pressure. This causes localized delamination. To calculate the forces required to de-bond the film, the ridges and buckles of the stressed film are measured. This test, like the blister test is impossible to perform routine measurements.
Scratch Test
Scratch testing involves dragging a sharp, metal-tipped tool or diamond on the film’s surface. The film’s pressure is increased until it fails. Acoustically, cracking is detected in the film when it is subject to load. Analyzing the failure parameters of known substrates and film combinations can reveal the adhesion, hardness, and modulus of a particular film. This tool is useful for developing work, but not for routine manufacturing process control.